1. Field of the Invention
The present invention relates to techniques for laying out power grids on integrated circuits, and more particularly, to techniques for routing supply voltage traces on integrated circuits that have a low voltage drop.
Power supply voltages are typically supplied to an integrated circuit from an external power supply source. The power supply voltages connect to the integrated circuit through bond pads on the integrated circuit. The power supply voltages are routed from the bond pads to transistors on the integrated circuit through metal traces formed in one or more metal layers.
Typically ring structures at the edges of the integrated circuit form the backbone of the power distribution system. The metal traces extend from the ring structures to the center of the integrated circuit in a serpentine fashion. The metal traces are then coupled to transistors in other layers of the integrated circuit. The traces used to route supply voltages to transistors at the center of an integrated circuit are substantially longer than the traces used to route the supply voltages to transistors near the edge of the integrated circuit.
The metal traces used to route power supply voltages into an integrated circuit have resistance. Because longer metal traces are used to route supply voltages and current to transistors that are farther away from the bond pads, transistors at the center of the integrated circuit receive a reduced supply voltage (VDD−VSS) relative to the supply voltage received by transistors near an edge of the integrated circuit. The magnitude of the voltage drop depends on the amount of current demanded as well as the size and the resistance of the conductors.
The speed of transistors is dependent in part on the magnitude of the power supply voltages they receive. Devices at the center of an integrated circuit may operate at reduced speeds, because they receive a reduced supply voltage. This can cause timing problems such as clock skew or increased propagation delay of gates and flip-flops. In larger integrated circuits, the reduction in the supply voltage can be even larger at the center of the chip.
Therefore, it would be desirable to provide techniques for routing power supply voltages within an integrated circuit that reduces voltage drop in the routing traces. It would also be desirable to provide techniques for routing power supply voltages within an integrated circuit that reduces the variations in the power supply voltages received in different regions of the integrated circuit.